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CS4299-BQ CS4299-BQ
CrystalClear(R)(R)SoundFusionTM Audio Codec `97 CrystalClear SoundFusionTM Audio Codec '97
Features
l AC
'97 2.1 Compatible Leading Mixed Signal Technology
l Industry l 20-bit l 18-bit
Stereo Digital-to-Analog Converters Stereo Analog-to-Digital Converters Rate Converters
or Exceeds the Microsoft(R) PC 99 Audio Performance Requirements l S/PDIF Digital Audio Output l CrystalClear(R) 3D Stereo Enhancement l Industrial Temperature Range
l Meets
Description
The CS4299-BQ is an AC '97 2.1 compatible stereo audio codec designed for PC multimedia systems. Using the industry leading CrystalClear(R) delta-sigma and mixed signal technology, the CS4299-BQ enables the design of PC 99-compliant desktop, portable, and entertainment PCs. Coupling the CS4299-BQ with a PCI audio accelerator or core logic supporting the AC '97 interface, implements a cost effective, superior quality, audio solution. The CS4299-BQ surpasses PC 99 and AC '97 2.1 audio quality standards. ORDERING INFO CS4299-BQZ lead-free 48-pin LQFP 9x9x1.4 mm
l Sample l Four l Two
Analog Line-level Stereo Inputs for LINE_IN, CD, VIDEO, and AUX Analog Line-level Mono Inputs for Modem and Internal PC Beep Stereo Line-level Outputs for LINE_OUT and ALT_LINE_OUT Microphone Inputs Quality Pseudo-Differential CD Input Power Management Support
AC-LINK AND AC '97 REGISTERS
l Dual l Dual l High
l Extensive
ANALOG INPUT MUX AND OUTPUT MIXER
TEST
PWR MGT SRC
SYNC BIT_CLK SDATA_OUT SDATA_IN RESET# ID0# ID1#
PCM_DATA
18 bit ADC
INPUT MUX
LINE CD AUX VIDEO MIC1 MIC2 PHONE PC_BEEP
ACLINK INPUT MIXER
GAIN / MUTE CONTROLS MIXER / MUX SELECTS
AC '97 REGISTERS
3D Stereo Enhancement OUTPUT MIXER
EAPD SPDIF_OUT
EAPD, S/PDIF
SRC
PCM_DATA
20 bit DAC
LINE_OUT ALT_LINE_OUT MONO_OUT
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512)http://www.cirrus.com 445 7581 445 7222 FAX: (512) http://www.cirrus.com
for a new product. Preliminary Product InformationThisThis document contains information for athis product without notice. Cirrus Logic reserves the right to modify new product. document contains information
Cirrus Logic reserves the right to modify this product without notice. MAR`06 Copyright (c) Inc. 2006 Copyright (c) Cirrus Logic, Cirrus Logic, Inc. 2006 March '06 DS319-BQPP2 (All Rights Reserved) (All Rights Reserved) DS319-BQPP2 1
CS4299-BQ CS4299-BQ
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 ANALOG CHARACTERISTICS ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 6 RECOMMENDED OPERATING CONDITIONS ....................................................................... 6 DIGITAL CHARACTERISTICS ................................................................................................. 6 AC '97 SERIAL PORT TIMING................................................................................................. 7 2. GENERAL DESCRIPTION ..................................................................................................... 10 2.1 AC-Link ............................................................................................................................ 10 2.2 Control registers .............................................................................................................. 10 2.3 Sample Rate Converters .................................................................................................. 11 2.4 Output Mixer .................................................................................................................... 11 2.5 Input Mux ......................................................................................................................... 11 2.6 Volume Control ................................................................................................................ 11 3. AC LINK FRAME DEFINITION ............................................................................................... 13 3.1 AC-Link Serial Data Output Frame .................................................................................. 14 3.1.1 Serial Data Output Slot Tags (Slot 0)............................................................................. 14 3.1.2 Command Address Port (Slot 1) .................................................................................... 15 3.1.3 Command Data Port (Slot 2).......................................................................................... 15 3.1.4 PCM Playback Data (Slots 3-10) ................................................................................... 15 3.2 AC-Link Audio Input Frame .............................................................................................. 16 3.2.1 Serial Data Input Slot Tag Bits (Slot 0) ......................................................................... 16 3.2.2 Status Address Port (Slot 1) .......................................................................................... 16 3.2.3 Status Data Port (Slot 2) ................................................................................................ 17 3.2.4 PCM Capture Data (Slot 3-10)....................................................................................... 17 3.3 AC-Link Protocol Violation - Loss of SYNC ..................................................................... 18 4. REGISTER INTERFACE ........................................................................................................ 19 4.1 Reset Register (Index 00h) .............................................................................................. 20 4.2 Master Volume Register (Index 02h) ............................................................................... 20 4.3 Alternate Volume Register (Index 04h) ............................................................................ 21 4.4 Mono Volume Register (Index 06h) ................................................................................. 21 4.5 PC_BEEP Volume Register (Index 0Ah) ......................................................................... 22 4.6 Phone Volume Register (Index 0Ch) ................................................................................ 22 4.7 Microphone Volume Register (Index 0Eh) ........................................................................ 23
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm
Microsoft is a registered trademark of Microsoft Corporation in the United States and/or other countries. Intel is a registered trademark of Intel Corporation. Crystal Clear and Sound Fusion are trademarks of Cirrus Logic. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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DS319-BQPP2
CS4299-BQ CS4299-BQ
4.8 Stereo Analog Mixer Input Gain Registers (Index 10h - 18h) ........................................... 24 4.9 Input Mux Select Register (Index 1Ah)............................................................................. 25 4.10 Record Gain Register (Index 1Ch) ................................................................................. 25 4.11 General Purpose Register (Index 20h) ........................................................................... 26 4.12 3D Control Register (Index 22h)..................................................................................... 26 4.13 Powerdown Control/Status Register (Index 26h) ........................................................... 27 4.14 Extended Audio ID Register (Index 28h) ........................................................................ 28 4.15 Extended Audio Status/Control Register (Index 2Ah) .................................................... 28 4.16 PCM Front DAC Rate Register (Index 2Ch) ................................................................ 29 4.17 PCM L/R ADC Rate Register (Index 32h) ...................................................................... 29 4.18 AC Mode Control Register (Index 5Eh) .......................................................................... 30 4.19 Misc. Crystal Control Register (Index 60h) ..................................................................... 30 4.20 S/PDIF Control Register (Index 68h)............................................................................. 31 4.21 Vendor ID1 Register (Index 7Ch) ................................................................................... 32 4.22 Vendor ID2 Register (Index 7Eh) ................................................................................... 32 5. POWER MANAGEMENT ....................................................................................................... 33 5.1 AC '97 Reset Modes ........................................................................................................ 33 5.1.1 Cold AC `97 Reset .............................................................................................. 33 5.1.2 Warm AC '97 Reset ............................................................................................ 33 5.1.3 Register AC '97 Reset ........................................................................................ 33 5.2 Powerdown Controls ....................................................................................................... 34 6. ANALOG HARDWARE DESCRIPTION ................................................................................. 36 6.1 Analog Inputs ................................................................................................................... 36 6.1.1 Line-Level Inputs ................................................................................................. 36 6.1.2 CD Input .............................................................................................................. 36 6.1.3 Microphone Inputs .............................................................................................. 37 6.1.4 PC Beep Input ..................................................................................................... 37 6.1.5 Phone Input ......................................................................................................... 38 6.2 Analog Outputs ................................................................................................................ 38 6.2.1 Stereo Outputs .................................................................................................... 38 6.2.2 Mono Output ....................................................................................................... 38 6.3 Miscellaneous Analog Signals ......................................................................................... 39 6.4 Power Supplies ................................................................................................................ 39 6.5 Reference Design ............................................................................................................ 39 7. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ................................................................... 40 8. GROUNDING AND LAYOUT ................................................................................................. 40 9. PIN DESCRIPTIONS ........................................................................................................... 42 ....................................................................................................... 49 10. PARAMETER AND TERM DEFINITIONS ............................................................................ 47 11. REFERENCE DESIGN 12. REFERENCES ...................................................................................................................... 50 13. PACKAGE DIMENSIONS .................................................................................................... 51 DS319-BQPP2 3 3
CS4299-BQ CS4299-BQ
LIST OF FIGURES
Figure 1. Power Up Timing.............................................................................................................. 8 Figure 2. Codec Ready from Startup or Fault Condition ................................................................. 8 Figure 3. Clocks .............................................................................................................................. 8 Figure 4. Data Setup and Hold........................................................................................................ 9 Figure 5. PR4 Powerdown and Warm Reset .................................................................................. 9 Figure 6. Test Mode ........................................................................................................................ 9 Figure 7. AC-link Connections....................................................................................................... 10 Figure 8. Mixer Diagram................................................................................................................ 12 Figure 9. AC-link Input and Output Framing.................................................................................. 13 Figure 10. Line Input (Replicate for Video and Aux) ..................................................................... 36 Figure 11. Differential 2 VRMS CD Input ...................................................................................... 36 Figure 12. Differential 1 VRMS CD Input ...................................................................................... 36 Figure 13. Microphone Input ......................................................................................................... 37 Figure 14. Microphone Pre-amplifier ............................................................................................. 37 Figure 15. PC_BEEP Input............................................................................................................ 37 Figure 16. Modem Connection ...................................................................................................... 38 Figure 17. Alternate Line Output as Headphone Output ............................................................... 38 Figure 18. Stereo Output............................................................................................................... 38 Figure 19. Voltage Regulator ........................................................................................................ 39 Figure 20. S/PDIF Output.............................................................................................................. 40 Figure 21. Conceptual Layout for the CS4299-BQ........................................................................ 41 Figure 22. Pin Locations for the CS4299-BQ ................................................................................ 42 Figure 23. CS4299 Reference Design .......................................................................................... 49
LIST OF TABLES
Table 1. Mixer Registers ...................................................................................................................... 19 Table 2. Analog Mixer Output Attenuation........................................................................................... 21 Table 3. Microphone Input Gain Values .............................................................................................. 23 Table 4. Analog Mixer Input Gain Values ............................................................................................ 24 Table 5. Stereo Volume Register Index ............................................................................................... 24 Table 6. Input Mux Selection ............................................................................................................... 25 Table 7. Standard Sample Rates......................................................................................................... 29 Table 8. Slot Mapping......................................................................................................................... 30 Table 9. Device ID with Corresponding Part Number .......................................................................... 32 Table 10. Revision Values ................................................................................................................... 32 Table 11. Powerdown PR Bit Functions .............................................................................................. 34 Table 12. Powerdown PR Function Matrix .......................................................................................... 35 Table 13. Power Consumption by Powerdown Mode .......................................................................... 35
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DS319-BQPP2
CS4299-BQ CS4299-BQ
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS Standard test conditions unless otherwise noted: Tambient = 25 C,
AVdd = 5.0 V 5%, DVdd = 3.3 V 5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; ZAL=100 k/ 1000 pF load, CDL = 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz, 18-bit linear coding for ADC functions, 20-bit linear coding for DAC functions; Mixer registers set for unity gain. CS4299-BQZ Parameter Symbol (Note 2) Full Scale Input Voltage Line Inputs Mic Inputs Mic Inputs (20 dB internal gain) Full Scale Output Voltage Line,Alternate Line, and Mono Outputs Frequency Response (Note 4) FR Analog Ac = 0.25 dB DAC Ac = 0.25 dB ADC Ac = 0.25 dB Dynamic Range DR Stereo Analog inputs to LINE_OUT Mono Analog inputs to LINE_OUT DAC Dynamic Range ADC Dynamic Range DAC SNR (-20 dB FS input w/ SNR CCIR-RMS filter on output) Total Harmonic Distortion + Noise THD+N (-3 dB FS input signal): Line/Alternate Line Output DAC ADC (all inputs except phone/mic) ADC (phone/mic) Power Supply Rejection Ratio (1 kHz, 0.5 VRMS w/ 5 V DC offset) (Note 4) Interchannel Isolation Spurious Tone Input Impedance External Load Impedance Output Impedance Input Capacitance Vrefout (Note 4) (Note 4) (Note 4) (Note 4) Path (Note 3) A-D A-D A-D D-A A-A D-A A-D A-A A-A D-A A-D D-A Min Typ Max Unit
0.85 20 20 20 -
1.00 1.00 0.10 1.0 90 85 85 80 70
1.15 20,000 20,000 20,000 -
VRMS VRMS VRMS VRMS Hz Hz Hz dB FS A dB FS A dB FS A dB FS A dB
A-A D-A A-D A-D
10 10 2.0
-72 -72 -72 -72 40 60 -100 730 5 2.28
2.5
dB FS dB FS dB FS dB FS dB dB dB FS k k pF V
Notes: 1. ZAL refers to the analog output pin loading and CDL refers to the digital output pin loading. 2. Parameter definitions are given in the Section 10, Parameter and Term Definitions. 3. Path refers to the signal path used to generate this data. These paths are defined in the Section 10, Parameter and Term Definitions. 4. This specification is guaranteed by silicon characterization, it is not production tested.
DS319-BQPP2
5 5
CS4299-BQ CS4299-BQ
ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)
Parameter Power Supplies Total Power Dissipation Input Current per Pin Output Current per Pin Analog Input voltage Digital Input voltage Ambient Temperature Storage Temperature (Power Applied) Digital Analog (Supplies, Inputs, Outputs) (Except Supply Pins) (Except Supply Pins) Min -0.3 -0.3 -10 -15 -0.3 -0.3 -40 -65 Typ 0.95 Max 5.5 5.5 1.25 10 15 AVdd + 0.3 DVdd + 0.3 85 150 Unit V V W mA mA V V C C
RECOMMENDED OPERATING CONDITIONS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)
Parameter Power Supplies Symbol +3.3 V Digital DVdd1, DVdd2 +5 V Digital DVdd1, DVdd2 Analog AVdd1, AVdd2 Min 3.135 4.75 4.75 -40 Typ 3.3 5 5 Max 3.465 5.25 5.25 85 Unit V V V C
Operating Ambient Temperature
DIGITAL CHARACTERISTICS (AVss = DVss = 0 V)
Parameter Symbol Low level input voltage Vil High level input voltage Vih High level output voltage Voh Low level output voltage Vol Input Leakage Current (AC-link inputs) Output Leakage Current (Tri-stated AC-link outputs) Output buffer drive current BIT_CLK, S/PDIF_OUT SDATA_IN, EAPD (Note 4) Min Typ Max 0.8 0.65 x DVdd 0.90 x DVdd 0.99 x DVdd 0.03 0.10 x DVdd -10 10 -10 10 24 4 Unit V V V V A A mA mA
6 6
DS319-BQPP2
CS4299-BQ CS4299-BQ
AC '97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: Tambient = 25 C,
AVdd = 5.0 V, DVdd = 3.3 V; CL = 55 pF load. Parameter RESET Timing RESET# active low pulse width RESET# inactive to BIT_CLK start-up delay 1st SYNC active to CODEC READY set Vdd stable to Reset inactive Clocks BIT_CLK frequency BIT_CLK period BIT_CLK output jitter (depends on XTAL_IN source) BIT_CLK high pulse width BIT_CLK low pulse width SYNC frequency SYNC period SYNC high pulse width SYNC low pulse width Data Setup and Hold Output Propagation delay from rising edge of BIT_CLK Input setup time from falling edge of BIT_CLK Input hold time from falling edge of BIT_CLK Input Signal rise time Input Signal fall time Output Signal rise time (Note 4) Output Signal fall time (Note 4) Misc. Timing Parameters End of Slot 2 to BIT_CLK, SDATA_IN low (PR4) SYNC pulse width (PR4) Warm Reset SYNC inactive (PR4) to BIT_CLK start-up delay Setup to trailing edge of RESET# (ATE test mode) (Note 4) Rising edge of RESET# to Hi-Z delay (Note 4) Symbol Trst_low Trst2clk Tsync2crd Tvdd2rst# Fclk Tclk_period Tclk_high Tclk_low Fsync Tsync_period Tsync_high Tsync_low Tco Tisetup Tihold Tirise Tifall Torise Tofall Ts2_pdown Tsync_pr4 Tsync2clk Tsetup2rst Toff Min 1.0 100 36 36 10 0 2 2 2 2 1.0 162.8 15 Typ 40.0 62.5 12.288 81.4 40.7 40.7 48 20.8 1.3 19.5 12 4 4 .28 285 Max 750 45 45 6 6 6 6 1.0 25 Unit s s s s MHz ns ps ns ns kHz s s s ns ns ns ns ns ns ns s s ns ns ns
DS319-BQPP2
7 7
CS4299-BQ CS4299-BQ
BIT_CLK Trst_low RESET# Tvdd2rst# Vdd
Figure 1. Power Up Timing
Trst2clk
BIT_CLK
SYNC Tsync2crd CODEC_READY
Figure 2. Codec Ready from Startup or Fault Condition
BIT_CLK Torise Tclk_high Tclk_low SYNC Tirise Tsync_high Tifall Tsync_low Tclk_period Tifall
Tsync_period
Figure 3. Clocks
8 8
DS319-BQPP2
CS4299-BQ CS4299-BQ
BIT_CLK
SDATA_IN Tco SDATA_OUT, SYNC
Tisetup
Figure 4. Data Setup and Hold
Tihold
BIT_CLK Slot 1 SDATA_OUT Write to 0x20 Slot 2 Data PR4 Ts2_pdown SDATA_IN Don't Care
SYNC Tsync_pr4 Tsync2clk
Figure 5. PR4 Powerdown and Warm Reset
RESET# Tsetup2rst SDATA_OUT, SYNC SDATA_IN, BIT_CLK
Figure 6. Test Mode DS319-BQPP2 9 9
Toff Hi-Z
CS4299-BQ CS4299-BQ
2. GENERAL DESCRIPTION
The CS4299-BQ is a mixed-signal serial audio Codec compliant to the Intel(R) Audio Codec `97 Specification, revision 2.1 [1]. It is designed to be paired with a digital controller, typically located on the PCI bus or integrated within the system core logic chip set. The controller is responsible for all communications between the CS4299-BQ and the remainder of the system. The CS4299-BQ contains two distinct functional sections: digital and analog. The digital section includes the AC-link interface, S/PDIF interface, serial data port, Sample Rate Converters, and power management support. The analog section includes the analog input multiplexer (mux), stereo output mixer, mono output mixer, stereo Analog-to-Digital Converters (ADCs), stereo Digital-to-Analog Converters (DACs), and their associated volume controls. ary audio codecs. Both input and output AC-link audio frames are organized as a sequence of 256 serial bits forming 13 groups referred to as `slots'. During each audio frame, data is passed bi-directionally between the CS4299-BQ and the controller. The input frame is driven from the CS4299-BQ on the SDATA_IN line. The output frame is driven from the controller on the SDATA_OUT line. The controller is also responsible for issuing reset commands via the RESET# signal. Following a Cold Reset, the CS4299-BQ is responsible for notifying the controller that it is ready for operation after synchronizing its internal functions. The CS4299-BQ AC-link signals must use the same digital supply voltage as the controller chip, either +5 V or +3.3 V. See Section 3, AC Link Frame Definition, for detailed AC-link information.
2.2
Control registers
2.1
AC-Link
All communication with the CS4299-BQ is established with a 5-wire digital interface to the controller, as shown in Figure 7. This interface is called the AC-link. All clocking for the serial communication is synchronous to the BIT_CLK signal. BIT_CLK is generated by the primary audio codec and is used to clock the controller and any second-
The CS4299-BQ contains a set of AC '97 compliant control registers and a set of Cirrus Logic defined control registers. These registers control the basic functions and features of the CS4299-BQ. Read accesses of the control registers by the AC '97 controller are accomplished with the requested register index in Slot 1 of a SDATA_OUT frame. The following SDATA_IN frame will con-
Digital AC'97 Controller
SYNC
BIT_CLK
CODEC
SDATA_OUT SDATA_IN RESET#
Figure 7. AC-link Connections 10 10 DS319-BQPP2
CS4299-BQ CS4299-BQ
tain the read data in its Slot 2. Write operations are similar, with the register index in Slot 1 and the write data in Slot 2 of a SDATA_OUT frame. The function of each input and output frame is detailed in Section 3, AC Link Frame Definition. Individual register descriptions are found in Section 4, Register Interface. ALT_LINE_OUT pins on the CS4299-BQ. The mono output mixer generates a monophonic sum of the left and right channels from the stereo input mixer. The mono output mix is sent to the MONO_OUT output pin on the CS4299-BQ.
2.5
Input Mux
2.3
Sample Rate Converters
The Sample Rate Converters (SRCs) provide high accuracy digital filters supporting sample frequencies other than 48 kHz to be captured from the CS4299 or played from the controller. AC '97 requires support for two audio rates (44.1 and 48kHz). In addition, the Intel(R) I/O Controller Hub (ICHx) specification requires support for five more audio rates (8, 11.025, 16, 22.05, and 32). The CS4299 supports all these rate, as shown in Table 7 on page 29.
The input multiplexer controls which analog input is sent to the ADCs. The output of the input mux is converted to stereo 18-bit digital PCM data and sent to the controller by means of the AC-link SDATA_IN signal.
2.6
Volume Control
2.4
Output Mixer
The CS4299-BQ has two output mixers, illustrated in Figure 8. The stereo output mixer sums together the analog inputs to the CS4299-BQ, including the PC_BEEP and PHONE signals, according to the settings in the volume control registers. The stereo output mix is sent to the LINE_OUT and
The CS4299-BQ volume registers control analog input levels to the input mixer and analog output levels, including the master volume level, and the alternate volume level. The PC_BEEP volume control uses 3 dB steps with a range of 0 dB to -45 dB attenuation. All other analog volume controls use 1.5 dB steps. The analog inputs have a mixing range of +12 dB signal gain to -34.5 dB signal attenuation. The analog output volume controls have from 0 dB to -94.5 dB attenuation for LINE_OUT and from 0 dB to -46.5 dB attenuation for ALT_LINE_OUT and MONO_OUT.
DS319-BQPP2
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CS4299-BQ CS4299-BQ
PC BEEP BYPASS PC_BEEP VOL
MUTE
PHONE
VOL
MUTE
MAIN D/A CONVERTERS PCM_OUT DAC MIC SELECT BOOST MUTE 3D DAC DIRECT MODE MASTER VOLUME OUTPUT BUFFER VOL LINE OUT VOL VOL MUTE
BYPASS BUFFER
MIC1 MIC2
LINE
MUTE
ANALOG STEREO INPUT MIXER
ANALOG STEREO OUTPUT MIXER
3D OUTPUT MIXER
MUTE
VOL
CD
VOL
MUTE
ALT LINE VOLUME ALT LINE OUT MUTE OUTPUT BUFFER VOL
VIDEO
VOL
MUTE
STEREO TO MONO MIXER
AUX
MUTE
1/2
MONO OUT SELECT
MONO VOLUME MONO OUT MUTE OUTPUT BUFFER VOL
VOL
STEREO TO MONO MIXER
1/2
MAIN ADC GAIN ADC INPUT MUX VOL MAIN A/D CONVERTERS PCM_IN
MUTE
ADC
Figure 8. Mixer Diagram
12 12
DS319-BQPP2
CS4299-BQ CS4299-BQ
3. AC LINK FRAME DEFINITION
The AC-link is a bidirectional serial port with data organized into frames consisting of one 16-bit and twelve 20-bit time-division multiplexed slots. The first slot, called the tag slot, contains bits indicating if the CS4299-BQ is ready to receive data (input frame) and which, if any, other slots contain valid data. Slots 1 through 12 contain audio or control/status data. Both the serial data output and input frames are defined from the controller perspective, not from the CS4299-BQ perspective. The controller synchronizes the beginning of a frame with the assertion of the SYNC signal. Figure 9 shows the position of each bit location within the frame. The first bit position in a new serial data frame is F0 and the last bit position in the serial data frame is F255. When SYNC goes active (high) and is sampled active by the CS4299-BQ (on the falling edge of BIT_CLK), both devices are synchronized to a new serial data frame. The data on the SDATA_OUT pin at this clock edge is the final bit of the previous frame's serial data. On the next rising edge of BIT_CLK, the first bit of Slot 0 is driven by the controller on the SDATA_OUT pin. On the next falling edge of BIT_CLK, the CS4299-BQ latches this data in, as the first bit of the frame.
20.8 s (48 kHz) Tag Phase SYNC 12.288 MHz 81.4 ns BIT_CLK Data Phase
Bit Frame Position:
F255 0
F0 Valid Frame
F1 Slot 1 Valid
F2 Slot 2 Valid
F12 Slot 12 Valid
F13
F14 Codec ID1
F15 Codec ID0
F16
F35
F36
F56
F57
F76
F96
F255
SDATA_OUT
0
R/W
0
WD15
D19
D18
D19
D19
0
Bit Frame Position:
F255 GPIO INT
F0 Codec Ready
F1 Slot 1 Valid
F2 Slot 2 Valid
F12 Slot 12 Valid
F13
F14
F15
F16
F35
F36
F56
F57
F76
F96
F255 GPIO INT
SDATA_IN
0
0
0
0
0
RD15
D19
D18
D19
D19
Slot 0
Slot 1
Slot 2
Slot 3
Slot 4
Slots 5-12
Figure 9. AC-link Input and Output Framing
DS319-BQPP2
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CS4299-BQ CS4299-BQ
3.1 AC-Link Serial Data Output Frame
In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4299-BQ from the AC '97 controller. Figure 9 illustrates the serial port timing. The PCM playback data being passed to the CS4299-BQ is shifted out MSB first in the most significant bits of each slot. Any PCM data from the AC '97 controller that is not 20 bits wide should be left justified in its corresponding slot and dithered or zero-padded in the unused bit positions. Bits that are reserved should always be `cleared' by the AC '97 controller. 3.1.1 Serial Data Output Slot Tags (Slot 0)
4 3 Reserved 2 1 0 Codec Codec ID1 ID0
Bit 15 14 13 12 11 10 9 8 7 6 5 Valid Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 Frame Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
Valid Frame
The Valid Frame bit determines if any of the following slots contain either valid playback data for the CS4299-BQ DACs or data for read/write operations. When `set', at least one of the other AC-link slots contain valid data. If this bit is `clear', the remainder of the frame is ignored. The Slot [1:2] Valid bits indicate the validity of data in their corresponding serial data output slots. If a bit is `set', the corresponding output slot contains valid data. If a bit is `cleared', the corresponding slot will be ignored. The Slot [3:10] Valid bits indicate Slot [3:10] contains valid playback data for the CS4299-BQ. If a Slot Valid bit is `set', the named slot contains valid audio data. If the bit is `clear', the slot will be ignored. The CS4299-BQ supports alternate slot mapping as defined in the AC '97 2.1 specification. For more information, see the AC Mode Control Register (Index 5Eh). The Codec ID[1:0] bits display the Codec ID of the audio codec being accessed during the current AC-link frame. Codec ID[1:0] = 00 indicates the primary codec is being accessed. Codec ID[1:0] = 01, 10, or 11 indicates one of three possible secondary codecs is being accessed. A non-zero value of one or more of the Codec ID bits indicates a valid Read or Write Address in Slot 1, and the Slot 1 R/W bit indicates presence or absence of valid Data in Slot 2.
Slot [1:2] Valid
Slot [3:10] Valid
Codec ID[1:0]
14 14
DS319-BQPP2
CS4299-BQ CS4299-BQ
3.1.2
Bit 19
Command Address Port (Slot 1)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W
RI6
RI5
RI4
RI3
RI2
RI1
RI0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
Read/Write. When this bit is `set', a read of the AC '97 register specified by the register index bits will occur in the AC '97 2.1 audio codec. When the bit is `cleared', a write will occur. For any read or write access to occur, the Frame Valid bit (F0) must be `set' and the Codec ID[1:0] bits (F[14:15]) must match the Codec ID of the AC '97 2.1 audio codec being accessed. Additionally, for a primary codec, the Slot 1 Valid bit (F1) must be `set' for a read access and both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be `set' for a write access. For a secondary codec, both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be `cleared' for read and write accesses. See Figure 9 for bit frame positions. Register Index. The RI[6:0] bits contain the 7-bit register index to the AC '97 registers in the CS4299-BQ. All registers are defined at word addressable boundaries. The RI0 bit must be `clear' to access CS4299-BQ registers.
RI[6:0]
3.1.3
Bit 19
Command Data Port (Slot 2)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
Reserved
WD[15:0] NOTE:
Write Data. The WD[15:0] bits contain the 16-bit value to be written to the register. If an access is a read, this slot is ignored. For any write to an AC '97 register, the write is defined to be an `atomic' access. This means that when the Slot 1 Valid bit in output Slot 0 is `set', the Slot 2 Valid bit in output slot 0 should always be `set' during the same audio frame. No write access may be split across 2 frames.
3.1.4
Bit 19
PCM Playback Data (Slots 3-10)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PD[19:0]
Playback Data. The PD[19:0] bits contain the 20-bit PCM playback (2's complement) data for the left and right DACs and/or the S/PDIF transmitter. Table 8 on page 30 lists a cross reference for each function and its respective slot. The mapping of a given slot to a DAC is determined by the state of the ID[1:0] bits in the Extended Audio ID Register (Index 28h) and by the SM[1:0] and AMAP bits in the AC Mode Control Register (Index 5Eh).
DS319-BQPP2
15 15
CS4299-BQ CS4299-BQ
3.2 AC-Link Audio Input Frame
In the serial data input frame, data is passed on the SDATA_IN pin from the CS4299-BQ to the AC '97 controller. The data format for the input frame is very similar to the output frame. Figure 9 on page 13 illustrates the serial port timing. The PCM capture data from the CS4299-BQ is shifted out MSB first in the most significant 18 bits of each slot. The least significant 2 bits in each slot will be `cleared'. If the host requests PCM data from the AC '97 Controller that is less than 18 bits wide, the controller should dither and round or just round (but not truncate) to the desired bit depth. Bits that are reserved or not implemented in the CS4299-BQ will always be returned `cleared'. 3.2.1 Serial Data Input Slot Tag Bits (Slot 0)
4 0 3 0 2 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 Codec Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 Ready Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
Codec Ready
The Codec Ready bit indicates the readiness of the CS4299-BQ AC-link. Immediately after a Cold Reset this bit will be `clear'. Once the CS4299-BQ clocks and voltages are stable, this bit will be `set'. Until the Codec Ready bit is `set', no AC-link transactions should be attempted by the controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any other analog function. Those must be checked in the Powerdown Control/Status Register (Index 26h) by the controller before any access is made to the mixer registers. Any accesses to the CS4299-BQ while Codec Ready is `clear' are ignored. When `set', the Slot 1 Valid bit indicates Slot 1 contains a valid read back address. When `set', the Slot 2 Valid bit indicates Slot 2 contains valid register read data. When `set', the Slot [3:10] Valid bits indicate Slot [3:10] contains valid capture data from the CS4299-BQ ADCs. Only if a Slot [3:10] Valid bit is `set' will the corresponding input slot contain valid data.
Slot 1 Valid Slot 2 Valid Slot [3:10] Valid
3.2.2
Bit 19
Status Address Port (Slot 1)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
RI6
RI5
RI4
RI3
RI2
RI1
RI0
SR3 SR4 SR5 SR6 SR7 SR8 SR9 SR10
0
Reserved
RI[6:0]
Register Index. The RI[6:0] bits echo the AC '97 register address when a register read has been requested in the previous frame. The CS4299-BQ will only echo the register index for a read access. Write accesses will not return valid data in Slot 1. Slot Request. If SRx is `set', this indicates the CS4299 SRC does not need a new sample on the next AC-link frame for that particular slot. If SRx is `clear', the SRC indicates a new sample is needed on the following frame. If the VRA bit in the Extended Audio Status/Control Register (Index 2Ah) is `clear', the SR[3:10] bits are always 0. When VRA is `set', the SRC is enabled and the SR[3:10] bits are used to request data. DS319-BQPP2
SR[3:10]
16 16
CS4299-BQ CS4299-BQ
3.2.3
Bit 19
Status Data Port (Slot 2)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
Reserved
RD[15:0]
Read Data. The RD[15:0] bits contain the register data requested by the controller from the previous read request. All read requests will return the read address in the input Slot 1 and the register data in the input Slot 2 on the following serial data frame.
3.2.4
Bit 19
PCM Capture Data (Slot 3-10)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
0
0
CD[17:0]
Capture Data. The D[17:0] bits contain 18-bit PCM (2's complement) capture data. The mapping of a given slot to an ADC is determined by the state of the ID[1:0] bits in the Extended Audio ID Register (Index 28h) and the SM[1:0] and AMAP bits in the AC Mode Control Register (Index 5Eh). The definition of each slot can be found in Table 8 on page 30.
DS319-BQPP2
17 17
CS4299-BQ CS4299-BQ
3.3 AC-Link Protocol Violation - Loss of SYNC
Upon loss of synchronization with the controller, the CS4299-BQ will `clear' the Codec Ready bit in the serial data input frame until two valid frames are detected. During this detection period, the CS4299-BQ will ignore all register reads and writes and will discontinue the transmission of PCM capture data. In addition, if the LOSM bit in the Misc. Crystal Control Register (Index 60h) is `set' (default), the CS4299-BQ will mute all analog outputs. If the LOSM bit is `clear', the analog outputs will not be muted.
The CS4299-BQ is designed to handle SYNC protocol violations. The following are situations where the SYNC protocol has been violated: * The SYNC signal is not sampled high for exactly 16 BIT_CLK clock cycles at the start of an audio frame. The SYNC signal is not sampled high on the 256th BIT_CLK clock period after the previous SYNC assertion. The SYNC signal goes active high before the 256th BIT_CLK clock period after the previous SYNC assertion.
*
*
18 18
DS319-BQPP2
CS4299-BQ CS4299-BQ
4. REGISTER INTERFACE
Reg Register Name D15 D14 D13 D12 D11 D10 D9
0 Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute 0 Mute 0 0 ID1 0 SE4 SE3 SE2 SE1 SE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID0 0 0
D8
ID8
D7
ID7 0 0 0 0 0 0 0 0 0 0 0 0 0
LPBK
D6
0 0 0 0 0 0
20dB
D5
0
D4
ID4
D3
0
D2
0
D1
0
D0 Default
0 1990h 8000h 8000h 8000h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 000Fh 0201h 0000h BB80h BB80h 0080h 0023h 0000h 4352h 5931h
00h Reset 02h Master Volume 04h Alternate Volume 06h Mono Volume 0Ah PC_BEEP Volume 0Ch Phone Volume 0Eh Mic Volume 10h Line In Volume 12h CD Volume 14h Video Volume 16h Aux Volume 18h PCM Out Volume 1Ah Record Select 1Ch Record Gain 20h General Purpose 22h 3D Control 26h Powerdown Ctrl/Stat 28h Extended Audio ID 2Ah Extended Audio Ctrl/Stat 2Ch PCM Front DAC Rate 32h PCM L/R ADC Rate 5E 60 68 AC Mode Control Misc. Crystal Control S/PDIF Control
ML5 ML4 ML3 ML2 ML1 ML0 ML5 ML4 ML3 ML2 ML1 ML0 0 0 0 0 0 0 0 0 0 0 0 3D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MR5 MR4 MR3 MR2 MR5 MR4 MR3 MR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PV3 PV2 PV1
MR1 MR0 MR1 MR0 PV0 GN1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 0 S1 0 0 SR1 SR1 0 0 GN0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 0 S0 VRA VRA SR0 SR0 0
LOSM
MM5 MM4 MM3 MM2 MM1 MM0 GN4 GN3 GN2 GN4 GN3 GN2 GR4 GR3 GR2 GR4 GR3 GR2 GR4 GR3 GR2 GR4 GR3 GR2 GR4 GR3 GR2 0 0 0 0 0 0 0 0 0 S3 REF 0 0 SR2 0 S2 ANL 0 0 SR2 SR2 0 GR3 GR2
GL4 GL3 GL2 GL1 GL0 GL4 GL3 GL2 GL1 GL0 GL4 GL3 GL2 GL1 GL0 GL4 GL3 GL2 GL1 GL0 GL4 GL3 GL2 GL1 GL0 0 0 0 0 0 0 0 0 0 0 0 SL2 0 0 0 0 SL1 MIX 0
AMAP
0 0 0 0 0 0 0 0 0 0 0 0
SL0 MS 0 0 0
GL3 GL2 GL1 GL0
0 0 0 0
EAPD PR6 PR5 PR4 PR3 PR2
PR1 PR0 0
DAC ADC
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR15 SR14 SR13 SR12 SR11 SR10 SR9
SR8 SR7 SR6 SR5 SR4 SR3 SR8 SR7 SR6 SR5 SR4 SR3
DDM AMAP
Cirrus Logic Defined Registers:
0 0
SPEN
0 0 Val F6 T6
0 0 0 F5 T5
0 0 Fs F4 T4
0 L F3 T3
0
0
0 0 S6
SM1 SM0 Reserved S5 S4
0 0 S3 0
Reserved F4 T2 F1 T1 F0 T0
0 S7 0
Reserved S2 S1
CC6 CC5 CC4 CC3 CC2 CC1 CC0 Emph Copy /Audio
DID2 DID1 DID0
Pro S0
7Ch Vendor ID1(CR) 7Eh Vendor ID2(Y-)
F7 T7
REV2 REV1 REV0
Table 1. Mixer Registers
DS319-BQPP2
19 19
CS4299-BQ CS4299-BQ
4.1
D15 0
Reset Register (Index 00h)
D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 0 D8 ID8 D7 ID7 D6 0 D5 0 D4 ID4 D3 0 D2 0 D1 0 D0 0
SE[4:0] ID8 ID7 ID4 Default
Crystal 3D Stereo Enhancement. SE[4:0] = 00110, indicating this feature is present. 18-bit ADC Resolution. The ID8 bit is `set', indicating this feature is present. 20-bit DAC resolution. The ID7 bit is `set', indicating this feature is present. Headphone Output (Alt Line Out). The ID4 bit is `set', indicating this feature is present. 1990h. The data in this register is read-only data.
Any write to this register causes a Register Reset to the default state of the audio (Index 00h - 38h) and vendor specific (Index 5Ah - 7Ah) registers. A read from this register returns configuration information about the CS429.
4.2
D15 Mute
Master Volume Register (Index 02h)
D14 0 D13 ML5 D12 ML4 D11 ML3 D10 ML2 D9 ML1 D8 ML0 D7 0 D6 0 D5 MR5 D4 MR4 D3 MR3 D2 MR2 D1 MR1 D0 MR0
Mute ML[5:0] MR[5:0] Default
Master Mute. Setting this bit mutes the LINE_OUT_L/R output signals. Master Volume Left. These bits control the left master output volume. Each step corresponds to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -94.5 dB attenuation. Master Volume Right. These bits control the right master output volume. Each step corresponds to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -94.5 dB attenuation. 8000h. This value corresponds to 0 dB attenuation and Mute `set'.
20 20
DS319-BQPP2
CS4299-BQ CS4299-BQ
4.3
D15 Mute
Alternate Volume Register (Index 04h)
D14 0 D13 ML5 D12 ML4 D11 ML3 D10 ML2 D9 ML1 D8 ML0 D7 0 D6 0 D5 MR5 D4 MR4 D3 MR3 D2 MR2 D1 MR1 D0 MR0
Mute ML[4:0]
Alternate Mute. Setting this bit mutes the ALT_LINE_OUT_L/R output signals. Alternate Volume Left. These bits control the left alternate output volume. Each step corresponds to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -46.5 dB attenuation. See Table 2 for further attenuation levels. Alternate Volume Left Max Attenuation. Setting ML5 sets the left channel attenuation to -46.5 dB by forcing ML[4:0] to a `1' state. ML[5:0] will read back 011111 when ML5 has been `set'. Table 2 summarizes this behavior. Alternate Volume Right. These bits control the right alternate output volume. Each step corresponds to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -46.5 dB attenuation. See Table 2 for further attenuation levels. Alternate Volume Right Max Attenuation. Setting MR5 sets the right channel attenuation to -46.5 dB by forcing MR[4:0] to a `1' state. MR[5:0] will read back 011111 when MR5 has been `set'. Table 2 summarizes this behavior. 8000h. This value corresponds to 0 dB attenuation and Mute `set'. Mx[5:0] Write 000000 000001 ... 011111 100000 ... 111111 Mx[5:0] Read 000000 000001 ... 011111 011111 ... 011111 Gain Level 0 dB -1.5 dB ... -46.5 dB -46.5 dB ... -46.5 dB
ML5
MR[4:0]
MR5
Default
Table 2. Analog Mixer Output Attenuation
4.4
D15 Mute
Mono Volume Register (Index 06h)
D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 MM5 D4 MM4 D3 MM3 D2 MM2 D1 MM1 D0 MM0
Mute MM[5:0]
Mono Mute. Setting this bit mutes the MONO_OUT signal. Mono Volume. These bits control the mono output volume. Each step corresponds to 1.5 dB gain adjustment, with a total available range from 0 dB to -46.5 dB attenuation. See Table 2 for further attenuation levels. Mono Volume Max Attenuation. Setting the MM5 bit sets the mono attenuation to -46.5 dB by forcing MM[4:0] to a `1' state. MM[5:0] will read back 011111 when MM5 has been `set'. Table 2 summarizes this behavior. 8000h. This value corresponds to 0 dB attenuation and Mute `set'. 21 21
MM5
Default DS319-BQPP2
CS4299-BQ CS4299-BQ
4.5
D15 Mute
PC_BEEP Volume Register (Index 0Ah)
D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 PV3 D3 PV2 D2 PV1 D1 PV0 D0 0
Mute PV[3:0]
PC_BEEP Mute. Setting this bit mutes the PC_BEEP input signal. PC_BEEP Volume Control. The PV[3:0] bits are used to control the gain levels of the PC_BEEP input source to the Input Mixer. Each step corresponds to 3 dB gain adjustment, with 0000 = 0 dB. The total range is 0 dB to -45 dB attenuation. 0000h. This value corresponds to 0 dB attenuation and Mute `clear'.
Default
This register has no effect on the PC_BEEP volume during RESET#.
4.6
D15 Mute
Phone Volume Register (Index 0Ch)
D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 GN4 D3 GN3 D2 GN2 D1 GN1 D0 GN0
Mute GN[4:0]
Phone Mute. Setting this bit mutes the Phone input signal. Phone Volume Control. The GN[4:0] bits are used to control the gain levels of the Phone input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 4 on page 24 for further details. 8008h. This value corresponds to 0 dB gain and Mute `set'.
Default
22 22
DS319-BQPP2
CS4299-BQ CS4299-BQ
4.7
D15 Mute
Microphone Volume Register (Index 0Eh)
D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 20dB D5 0 D4 GN4 D3 GN3 D2 GN2 D1 GN1 D0 GN0
Mute GN[4:0]
Microphone Mute. Setting this bit mutes the MIC1 or MIC2 signal. The selection of the MIC1 or MIC2 input pin is controlled by the MS bit in the General Purpose Register (Index 20h). Microphone Volume Control. The GN[4:0] bits are used to control the gain level of the Microphone input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 3 for further details. Microphone 20 dB Boost. When `set', the 20dB bit enables the +20 dB microphone boost block. This bit allows for variable boost of 0 dB or +20 dB. Table 3 summarizes this behavior. 8008h. This value corresponds to 0 dB gain and Mute `set'. Gain Level 20dB = 0 +12.0 dB +10.5 dB ... +1.5 dB 0.0 dB -1.5 dB ... -34.5 dB 20dB = 1 +32.0 dB +30.5 dB ... +21.5 dB +20.0 dB +18.5 dB ... -14.5 dB
20dB Default
GN[4:0] 00000 00001 ... 00111 01000 01001 ... 11111
Table 3. Microphone Input Gain Values
DS319-BQPP2
23 23
CS4299-BQ CS4299-BQ
4.8
D15 Mute
Stereo Analog Mixer Input Gain Registers (Index 10h - 18h)
D14 0 D13 0 D12 GL4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 0 D6 0 D5 0 D4 GR4 D3 GR3 D2 GR2 D1 GR1 D0 GR0
Mute GL[4:0]
Stereo Input Mute. Setting this bit mutes the respective input signal, both right and left inputs. Left Volume Control. The GL[4:0] bits are used to control the gain level of the left analog input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 4 for further details. Right Volume Control. The GR[4:0] bits are used to control the gain level of the right analog input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 4 for further details. 8808h. This value corresponds to 0 dB gain and Mute `set'.
GR[4:0]
Default
The Stereo Analog Mixer Input Gain Registers are listed in Table 5. Gx[4:0] 00000 00001 ... 00111 01000 01001 ... 11111 Gain Level +12.0 dB +10.5 dB ... +1.5 dB 0.0 dB -1.5 dB ... -34.5 dB
Table 4. Analog Mixer Input Gain Values Register Index 10h 12h 14h 16h 18h Function Line In Volume CD Volume Video Volume Aux Volume PCM Out Volume
Table 5. Stereo Volume Register Index
24 24
DS319-BQPP2
CS4299-BQ CS4299-BQ
4.9
D15 0
Input Mux Select Register (Index 1Ah)
D14 0 D13 0 D12 0 D11 0 D10 SL2 D9 SL1 D8 SL0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 SR2 D1 SR1 D0 SR0
SL[2:0] SR[2:0] Default
Left Channel Source. The SL[2:0] bits select the left channel source to pass to the ADCs for recording. See Table 6 for possible values. Right Channel Source. The SR[2:0] bits select the right channel source to pass to the ADCs for recording. See Table 6 for possible values. 0000h. This value selects the Mic input for both channels. Sx[2:0] 000 001 010 011 100 101 110 111 Record Source Mic CD Input Video Input Aux Input Line Input Stereo Mix Mono Mix Phone Input
Table 6. Input Mux Selection
4.10
D15 Mute
Record Gain Register (Index 1Ch)
D14 0 D13 0 D12 0 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 0 D6 0 D5 0 D4 0 D3 GR3 D2 GR2 D1 GR1 D0 GR0
Mute GL[3:0]
Record Gain Mute. Setting this bit mutes the input to the L/R ADCs. Left ADC Gain. The GL[3:0] bits control the input gain on the left channel of the analog source, applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB gain adjustment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain. Right ADC Gain. The GR[3:0] bits control the input gain on the right channel of the analog source, applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB gain adjustment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain. 8000h. This value corresponds to 0 dB gain and Mute `set'.
GR[3:0]
Default
DS319-BQPP2
25 25
CS4299-BQ
4.11
D15 0
General Purpose Register (Index 20h)
D14 0 D13 3D D12 0 D11 0 D10 0 D9 MIX D8 MS D7 LPBK D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
3D MIX MS LPBK Default
3D Enable. When `set', the 3D bit enables the CrystalClearTM 3D stereo enhancement. This function is not available in DAC Direct Mode (DDM). Mono Output Select. The MIX bit selects the source for the Mono Out output. When `set', the microphone input is selected. When `clear', the stereo-to-mono mixer is selected. Microphone Select. The MS bit determines which of the two Mic inputs are passed to the mixer. When `set', the MIC2 input is selected. When `clear', the MIC1 input is selected. Loopback Enable. When `set', the LPBK bit enables the ADC/DAC Loopback Mode. This bit routes the output of the ADCs to the input of the DACs without involving the AC-link. 0000h
4.12
D15 0
3D Control Register (Index 22h)
D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 S3 D2 S2 D1 S1 D0 S0
S[3:0]
Spacial Enhancement Depth. These bits control the amount of "space" added to the output stereo signal. When S[3:0] = 0000, the minimum amount of spatial enhancement is added. When S[3:0] = 1111, the maximum amount of spatial enhancement is added. The 3D function is enabled and disabled by the 3D bit in the General Purpose Register (Index 20h). 0000h. This value corresponds to minimum spatial enhancement added to the output signal.
Default
26
CS4299-BQ CS4299-BQ
4.13
D15 EAPD
Powerdown Control/Status Register (Index 26h)
D14 PR6 D13 PR5 D12 PR4 D11 PR3 D10 PR2 D9 PR1 D8 PR0 D7 0 D6 0 D5 0 D4 0 D3 REF D2 ANL D1 DAC D0 ADC
EAPD
External Amplifier Power Down. The EAPD pin follows this bit and is generally used to power down external amplifiers. Alternate Line Out Powerdown. When `set', the alternate line out buffer is powered down. Internal Clock Disable. When `set', this bit completely powers down both the analog and digital sections of the CS4299-BQ. The only way to recover from setting this bit is through a Cold Reset (driving the RESET# signal active). AC-link Powerdown. When `set', the AC link is powered down (BIT_CLK off). The AC-link can be restarted through a Warm Reset using the SYNC signal, or a Cold Reset using the RESET# signal (primary audio codec only). Analog Mixer Powerdown (Vref off). When `set', the analog mixer and voltage reference are powered down. When clearing this bit, the ANL, ADC, and DAC bits should be checked before writing any mixer registers. Analog Mixer Powerdown (Vref on). When `set', the analog mixer is powered down (the voltage reference is still active). When clearing this bit, the ANL bit should be checked before writing any mixer registers. Front DACs Powerdown. When `set', the DACs are powered down. When clearing this bit, the DAC bit should be checked before sending any data to the DACs. L/R ADCs and Input Mux Powerdown. When `set', the ADCs and the ADC input muxes are powered down. When clearing this bit, no valid data will be sent down the AC link until the ADC bit goes high. Voltage Reference Ready Status. When `set', indicates the voltage reference is at a nominal level. Analog Ready Status. When `set', the analog output mixer, input multiplexer, and volume controls are ready. When clear, no volume control registers should be written. Front DAC Ready Status. When `set', the DACs are ready to receive data across the AC link. When clear, the DACs will not accept any valid data. L/R ADC Ready Status. When `set', the ADCs are ready to send data across the AC link. When clear, no data will be sent to the Controller. 0000h. This value indicates all blocks are powered on. The lower four bits will change as the CS4299-BQ finishes an initialization and calibration sequence.
PR6 PR5
PR4
PR3
PR2
PR1
PR0
REF
ANL
DAC
ADC
Default
The PR[6:0] and the EAPD bits are powerdown control for different sections of the CS4299-BQ as well as external amplifiers. The REF, ANL, DAC, and ADC bits are read-only status bits which, when `set', indicate that a particular section of the CS4299-BQ is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must be checked before writing to any mixer registers. See Section 5, Power Management, for more information on the powerdown functions. DS319-BQPP2 27 27
CS4299-BQ CS4299-BQ
4.14
D15 ID1
Extended Audio ID Register (Index 28h)
D14 ID0 D13 0 D12 0 D11 0 D10 0 D9 AMAP D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 VRA
ID[1:0]
Codec Configuration ID. When ID[1:0] = 00, the CS4299-BQ is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4299-BQ is a secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins. Audio Slot Mapping. The AMAP bit indicates whether the optional AC '97 2.1 compliant AC-link slot to audio DAC mapping is supported. This bit is a shadow of the AMAP bit in the AC Mode Control Register (Index 5Eh). The PCM playback and capture slots are mapped according to Table 8 on page 30. Variable Rate PCM Audio. The VRA bit indicates whether variable rate PCM audio is supported. This bit always returns `1', indicating that variable rate PCM audio is available. x201h. Where x is determined by the state of ID[1:0]# input pins. The Extended Audio ID Register (Index 28h) is a read only register.
AMAP
VRA Default
4.15
D15 0
Extended Audio Status/Control Register (Index 2Ah)
D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 VRA
VRA
Enable Variable Rate Audio. When `set', the VRA bit allows access to the PCM Front DAC Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h). The bit must be `set' in order to use variable PCM playback or capture rates. The VRA bit also serves as a powerdown for the DAC and ADC SRC blocks. Clearing VRA will reset the PCM Front DAC Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) to their default values. The SRC data path is flushed and the Slot Request bits for the currently active DAC slots will be fixed at `0'. 0000h
Default
28 28
DS319-BQPP2
CS4299-BQ CS4299-BQ
4.16 PCM Front DAC Rate Register (Index 2Ch)
D13 D12 SR13 SR12 D11 D10 SR11 SR10 D9 SR9 D8 SR8 D7 SR7 D6 SR6 D5 SR5 D4 SR4 D3 SR3 D2 SR2 D1 SR1 D0 SR0
D15 D14 SR15 SR14
SR[15:0]
Front DAC Sample Rate. The SR[15:0] bits can only be written when the VRA bit of the Extended Audio Status/Control Register (Index 2Ah) is `set'. If the VRA bit is `clear', all writes are ignored and the register reads back BB80h; corresponding to a 48 kHz sample rate. If the VRA bit is `set', seven standard sample rates are available. If a sample rate written to the register is not directly supported, the attempted value to be written will be decoded according to the ranges indicated in Table 7. All register read transactions will reflect the actual value stored (column 2 in Table 7) and not the one attempted to be written. BB80h. This value corresponds to 48 kHz sample rate.. Sample rate (Hz)
8,000 11,025 16,000 22,050 32,000 44,100 48,000
Default
SR[15:0]
1F40 2B11 3E80 5622 7D00 AC44 BB80
SR[15:12] Decode Range
0 or 1 2 3 4 or 5 6 or 7 8, 9, or Ah Bh, Ch, Dh, Eh, or Fh
Table 7. Standard Sample Rates
4.17
PCM L/R ADC Rate Register (Index 32h)
D13 D12 SR13 SR12 D11 D10 SR11 SR10 D9 SR9 D8 SR8 D7 SR7 D6 SR6 D5 SR5 D4 SR4 D3 SR3 D2 SR2 D1 SR1 D0 SR0
D15 D14 SR15 SR14
SR[15:0]
Left/Right ADC Sample Rate. The SR[15:0] bits can only be written when the VRA bit of the Extended Audio Status/Control Register (Index 2Ah) is `set'. If the VRA bit is `clear', all writes are ignored and the register reads back BB80h; corresponding to a 48 kHz sample rate. If the VRA bit is `set', seven standard sample rates are available. If a sample rate written to the register is not directly supported, the attempted value to be written will be decoded according to the ranges indicated in Table 7. All register read transactions will reflect the actual value stored (column 2 in Table 7) and not the one attempted to be written. BB80h. This value corresponds to 48 kHz sample rate.
Default
DS319-BQPP2
29 29
CS4299-BQ CS4299-BQ
4.18
D15 0
AC Mode Control Register (Index 5Eh)
D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 D7 DDM AMAP D6 0 D5 SM1 D4 SM0 D3 0 D2 0 D1 0 D0 0
DDM
DAC Direct Mode. This bit controls the source to the line and alternate line output drivers. When `set', the L/R DACs directly drive the line and alternate line outputs by bypassing the audio mixer. When `clear', the audio mixer is the source for the line and alternate line outputs. Audio Slot Mapping. This read/write bit controls whether the CS4299-BQ responds to the Codec ID based slot mapping as outlined in the AC '97 2.1 specification. The bit is shadowed in the Extended Audio ID Register (Index 28h). Refer to Table 8 for the slot mapping configurations. Slot Map. The SM[1:0] bits define the Slot Mapping for the CS4299-BQ when the AMAP bit is `cleared'. Refer to Table 8 for the slot mapping configurations. 0080h Codec ID Slot Assignment Mode AMAP Mode 0 AMAP Mode 1 AMAP Mode 2 AMAP Mode 3 Slot Map Mode 0 Slot Map Mode 1 Slot Map Mode 2 Slot Map Mode 3 Slot Map AMAP Slot Assignments DAC, SPDIF L 0 0 1 1 X X X X 0 1 0 1 X X X X X X X X 0 0 1 1 X X X X 0 1 0 1 1 1 1 1 0 0 0 0 3 3 7 6 3 5 7 9 R 4 4 8 9 4 6 8 10 L 3 3 7 6 3 5 7 9 ADC R 4 4 8 9 4 6 8 10
AMAP
SM[1:0] Default
ID1 ID0 SM1 SM0
Table 8. Slot Mapping
4.19
D15 0
Misc. Crystal Control Register (Index 60h)
D14 0 D13 0 D12 0 D11 D10 D9 Reserved D8 D7 0 D6 0 D5 D4 Reserved D3 0 D2 D1 Reserved D0 LOSM
LOSM
Loss of SYNC Mute Enable. The LOSM bit controls the loss of SYNC mute function. If this bit is `set', the CS4299-BQ will mute all analog outputs for the duration of loss of SYNC. If this bit is `cleared', the mixer will continue to function normally during loss of SYNC. The CS4299-BQ expects to sample SYNC `high' for 16 consecutive BIT_CLK periods and then `low' for 240 consecutive BIT_CLK periods, otherwise loss of SYNC becomes true. 0023h
Default
30 30
DS319-BQPP2
CS4299-BQ CS4299-BQ
4.20
D15 SPEN
S/PDIF Control Register (Index 68h)
D14 Val D13 0 D12 Fs D11 L D10 CC6 D9 CC5 D8 CC4 D7 CC3 D6 CC2 D5 CC1 D4 CC0 D3 Emph D2 D1 Copy /Audio D0 Pro
SPEN
S/PDIF Enable. The SPEN bit enables S/PDIF data transmission on the S/PDIF_OUT pin. The SPEN bit routes the left and right channel data from the AC '97 controller, the digital mixer, or the digital effects engine to the S/PDIF transmitter block. The actual data routed to the S/PDIF block is controlled through the AMAP/SM[1:0] configuration in the AC Mode Control Register (Index 5Eh). Validity. The V bit is mapped to the V bit (bit 28) of every sub-frame. If this bit is `0', the signal is suitable for conversion or processing. Sample Rate. The Fs bit indicates the sampling rate for the S/PDIF data. The inverse of this bit is mapped to bit 25 of the channel status block. When the Fs bit is `clear', the sampling frequency is 48 kHz. When `set', the sampling frequency is 44.1 kHz. The actual rate at which S/PDIF data are being transmitted solely depends on the master clock frequency of the CS4299-BQ. The Fs bit is merely an indicator to the S/PDIF receiver. Generation Status. The L bit is mapped to bit 15 of the channel status block. For category codes 001xxxx, 0111xxx and 100xxxx, a value of `0' indicates original material and a value of `1' indicates a copy of original material. For all other category codes the definition of the L bit is reversed. Category Code. The CC[6:0] bits are mapped to bits 8-14 of the channel status block. Data Emphasis. The Emph bit is mapped to bit 3 of the channel status block. If the Emph bit is `1', 50/15us filter pre-emphasis is indicated. If the bit is `0', no pre-emphasis is indicated. Copyright. The Copy bit is mapped to bit 3 of the channel status block. If the Copy bit is `1' copyright is not asserted and copying is permitted. Audio / Non-Audio. The /Audio bit is mapped to bit 1 of the channel status block. If the /Audio bit is `0', the data transmitted over S/PDIF is assumed to be digital audio. If the /Audio bit is `1', non-audio data is assumed. Professional/Consumer. The Pro bit is mapped to bit 0 of the channel status block. If the Pro bit is `0', consumer use of the audio control block is indicated. If the bit is `1', professional use is indicated. 0000h
Val Fs
L
CC[6:0] Emph Copy /Audio
Pro
Default
For a further discussion of the proper use of the channel status bits see application note AN22: Overview of Digital Audio Interface Data Structures [3].
DS319-BQPP2
31 31
CS4299-BQ CS4299-BQ
4.21
D15 F7
Vendor ID1 Register (Index 7Ch)
D14 F6 D13 F5 D12 F4 D11 F3 D10 F2 D9 F1 D8 F0 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0
F[7:0] S[7:0] Default
First Character of Vendor ID. With a value of F[7:0] = 43h, these bits define the ASCII `C' character. Second Character of Vendor ID. With a value of S[7:0] = 52h, these bits define the ASCII `R' character. 4352h. This register contains read-only data.
4.22
D15 T7
Vendor ID2 Register (Index 7Eh)
D14 T6 D13 T5 D12 T4 D11 T3 D10 T2 D9 T1 D8 T0 D7 0 D6 DID2 D5 DID1 D4 DID0 D3 0 D2 D1 D0 REV2 REV1 REV0
T[7:0] DID[2:0] REV[2:0] Default
Third Character of Vendor ID. With a value of T[7:0] = 59h, these bits define the ASCII `Y' character. Device ID. With a value of DID[2:0] = 011, these bits specify the audio codec is a CS4299. Revision. With a value of REV[2:0] = 001, these bits specify the audio codec revision is `A'. 593xh. This register contains read-only data.
The two Vendor ID registers provide a means to determine the manufacturer of the AC '97 audio codec. The first three bytes of the Vendor ID registers contain the ASCII code for the first three letters of Crystal (CRY). The final byte of the Vendor ID registers is divided into a Device ID field and a Revision field. Table 9 lists the currently defined Device ID's. Table 10 lists the current revisions of the CS4299-BQ. DID[2:0] 000 001 010 011 100 101 110 111 Part Name CS4297 CS4297A CS4294/CS4298 CS4299 CS4201 CS4205 CS4291 CS4202
Table 9. Device ID with Corresponding Part Number REV[2:0] 001 010 011 100 101 110 Revision A B C D, E, F, G, H K L
Table 10. Revision Values 32 32 DS319-BQPP2
CS4299-BQ CS4299-BQ
5. POWER MANAGEMENT 5.1 AC '97 Reset Modes
The CS4299-BQ supports three reset methods, as defined in the AC '97 Specification: Cold AC '97 Reset, Warm AC '97 Reset, Register AC '97 Reset. A Cold Reset results in all AC '97 logic (registers included) initialized to its default state. A Warm Reset leaves the contents of the AC '97 register set unaltered. A Register Reset initializes only the AC '97 registers to their default states.
5.1.2
Warm AC '97 Reset
5.1.1
Cold AC `97 Reset
A Cold Reset is achieved by asserting RESET# for a minimum of 1 s after the power supply rails have stabilized. This is done in accordance with the minimum timing specifications in the AC '97 Serial Port Timing section on page 7. Once deasserted, all of the CS4299-BQ registers will be reset to their default power-on states and the BIT_CLK and SDATA_IN signals will be reactivated.
A Warm Reset allows the AC-link to be reactivated without losing information in the CS4299-BQ registers. A Warm Reset is required to resume from a D3hot state, where the AC-link had been halted yet full power had been maintained. A primary codec Warm Reset is initiated when the SYNC signal is driven high for at least 1 s and then driven low in the absence of the BIT_CLK clock signal. The BIT_CLK clock will not restart until at least 2 normal BIT_CLK clock periods (162.8 ns) after the SYNC signal is deasserted. A Warm Reset of the secondary codec is recognized when the primary codec on the AC-link resumes BIT_CLK generation. The CS4299-BQ will wait for BIT_CLK to be stable to restore SDATA_IN activity and/or S/PDIF transmission on the following frame.
5.1.3
Register AC '97 Reset
The third reset mode provides a Register Reset to the CS4299-BQ. This is available only when the CS4299-BQ AC-link is active and the Codec Ready bit is `set'. The audio (including extended audio) registers (Index 00h - 38h) and the vendor specific registers (Index 5Ah - 7Ah) are reset to their default states by a write of any value to the Reset Register (Index 00h).
DS319-BQPP2
33 33
CS4299-BQ CS4299-BQ
5.2 Powerdown Controls
SDATA_OUT in their normal capacities. Either a Cold Reset or a Warm Reset is required to restore operation to the CS4299-BQ. A Cold Reset will restore all mixer registers to their power-on default values. A Warm Reset will not alter the values of any mixer register, except clearing the PR4 bit in Powerdown Control/Status Register (Index 26h). The PR5 bit powers down all analog and digital subsections of the device. A Cold Reset is the only way to restore operation to the CS4299-BQ after a PR5 global powerdown. The CS4299-BQ does not automatically mute any input or output when the powerdown bits are `set'. The software driver controlling the AC '97 device must manage muting the input and output analog signals before putting the part into any power management state. The definition of each PRx bit may affect a single subsection or a combination of subsections within the CS4299-BQ. Table 12 on page 35 contains the matrix of subsections affected by the respective PRx function. Table 13 on page 35 shows the different operating power consumptions levels for different powerdown functions.
Function L/R ADCs and Input Mux Powerdown Front DACs Powerdown Analog Mixer Powerdown (Vref on) Analog Mixer Powerdown (Vref off) AC-link Powerdown (BIT_CLK off)* Internal Clock Disable Alternate Line Out Powerdown
The Powerdown Control/Status Register (Index 26h) controls the power management functions. The PR[6:0] bits in this register control the internal powerdown states of the CS4299-BQ. Powerdown control is available for individual subsections of the CS4299-BQ by asserting any PRx bit or any combination of PRx bits. Most powerdown states can be resumed by clearing the corresponding PRx bit. Table 11 shows the mapping of the power control bits to the functions they manage. When PR0 is `set', the L/R ADCs and the Input Mux are shut down and the ADC bit in the Powerdown Control/Status Register (Index 26h) is `cleared' indicating the ADCs are no longer in a ready state. The same is true for the DACs, the analog mixers, and the reference voltage (Vrefout). When the PR2 or PR3 bit of the mixer is `cleared', the mixer section will begin a power-on process, and the corresponding powerdown status bit will be `set' when the hardware is ready. Shutting down the AC-link by `setting' PR4 causes the primary Codec to turn off the BIT_CLK and drive SDATA_IN low. It also ignores SYNC and
PR Bit PR0 PR1 PR2 PR3 PR4 PR5 PR6
* Applies only to primary codec Table 11. Powerdown PR Bit Functions
34 34
DS319-BQPP2
CS4299-BQ CS4299-BQ
PR Bit PR0 PR1 PR2 PR3 PR4 PR5 PR6
ADCs
DACs
Mixer
Alternate Line Out
Analog Reference
AC Link
Internal Clock Off
* * * * * * * * * * * *
* *
* * * * *
Table 12. Powerdown PR Function Matrix
Power State Full Power + SRC's Full Power + S/PDIF Full Power ADCs off (PR0) DACs off (PR1) Audio off (PR2) Vref off (PR3) AC-Link off (PR4) Internal Clocks off (PR5) Alt line out off (PR6) RESET
1
IDVdd (mA) [DVdd=3.3 V] 29.1
1
IDVdd (mA) [DVdd=5 V] 50.2 49.4 43.4 38.1 39.6 39.9 34.8 35.5 27 A 43.4 27 A
IAVdd (mA) 37.9 37.9 37.9 29.0 31.3 10.7 45 A 37.9 45 A 36.2 450 A
30.1 24.5 21.0 22.1 22.1 18.9 19.3 11 A 24.5 11 A
Table 13. Power Consumption by Powerdown Mode
Assuming standard resistive load for transformer coupled coaxial S/PDIF output (Rload = 292 Ohm, DVdd = 3.3 V) (Rload = 415 Ohm, DVdd = 5 V). General: IDVdd S/PDIF = IDVdd + DVdd/Rload/2
DS319-BQPP2
35 35
CS4299-BQ CS4299-BQ
6. ANALOG HARDWARE DESCRIPTION
The analog line-level input hardware consists of four stereo inputs (LINE_IN_L/R, CD_L/GND/R, VIDEO_L/R, and AUX_L/R), two selectable mono microphone inputs (MIC1 and MIC2), and two mono inputs (PC_BEEP and PHONE). The analog line-level output hardware consists of a mono output (MONO_OUT), and dual stereo line outputs (LINE_OUT_L/R and ALT_LINE_OUT_L/R). This section describes the analog hardware needed to interface with these pins. The designs presented in this section comply with specifications detailed in Chapter 17 of the Microsoft(R) PC Design Guidelines [7] (referred to as PC 99). For EMI reduction techniques refer to the application note AN165: CS4297A/CS4299 EMI Reduction Techniques [5]. connected to the CD analog source ground. Following the reference designs in Figure 11 and Figure 12 provides extra attenuation of common mode noise coming from the CD-ROM drive, thereby producing a higher quality signal. One percent resistors are recommended since closely matched resistor values provide better common-mode attenuation of unwanted signals. The circuit shown in Figure 11 can be used to attenuate a 2 VRMS CD input signal by 6 dB. The circuit shown in Figure 12 can be used for a 1 VRMS CD input signal.
6.8 k 1.0 F R 1.0 F 6.8 k 6.8 k 6.8 k L
6.1
Analog Inputs
All analog inputs to the CS4299-BQ, including CD_GND, should be capacitively coupled to the input pins. Unused analog inputs should be tied together and connected through a capacitor to analog ground or tied to the Vrefout pin directly. The maximum allowed voltage for analog inputs, except the microphone input, is 1 VRMS. For the microphone input the maximum allowed voltage depends on the selected boost setting.
Figure 10. Line Input (Replicate for Video and Aux)
CD_R CD_L CD_COM
6.8 k 6.8 k 3.4 k 6.8 k (All resistors 1%) 6.8 k
1.0 F 1.0 F 2.2 F CD_R CD_L CD_GND 3.4 k
6.1.1
Line-Level Inputs
AGND
Figure 10 shows circuitry for a line-level stereo input. Replicate this circuit for the Line, Video and Aux inputs. This design attenuates the input by 6 dB, bringing the signal from the PC 99 specified 2 VRMS, to the CS4299-BQ maximum allowed 1 VRMS.
Figure 11. Differential 2 VRMS CD Input
CD_R CD_L CD_COM
100 100 100 47 k 47 k
1.0 F 1.0 F 2.2 F
CD_R CD_L CD_GND
6.1.2
CD Input
47 k
The CD line-level input has an extra pin, CD_GND, providing a pseudo-differential input for both CD_L and CD_R. This pin takes the common-mode noise out of the CD inputs when
36 36
AGND
Figure 12. Differential 1 VRMS CD Input
DS319-BQPP2
CS4299-BQ CS4299-BQ
6.1.3 Microphone Inputs 6.1.4 PC Beep Input
Figure 13 illustrates an input circuit suitable for dynamic and electret microphones. Electret, or phantom-powered, microphones use the right channel (ring) of the jack for power. The design also supports the recommended advanced frequency response for voice recognition as specified in PC 99. Note the microphone input to the CS4299-BQ has an integrated pre-amplifier. Using the 20dB bit in the Microphone Volume Register (Index 0Eh) the pre-amplifier gain can be set to 0 dB or 20 dB. Figure 14 shows an external pre-amplifier circuit for an additional 18 dB gain.
2 k + 0.1 F Vrefout
The PC_BEEP input is useful for mixing the output of the "beeper" (timer chip), provided in most PCs, with the other audio signals. When the CS4299-BQ is held in reset, PC_BEEP is passed directly to the line output. This allows the system sounds or "beeps" to be available before the AC '97 interface has been activated. Figure 15 illustrates a typical input circuit for the PC_BEEP input. If PC_BEEP is driven from a CMOS gate, the 4.7 k resistor should be tied to analog ground instead of +5VA. Although this input is described for a low-quality "beeper", it is of the same high-quality as all other analog inputs and may be used for other purposes.
+5VA (Low Noise) or AGND if CMOS Source
47 k 0.33 F 47 100 pF NPO
1 F
MC33078 or MC33178
0.33 F X7R
47 k 220 pF NPO 3.3 F
MIC1 or MIC2
47 k PC-BEEP-BUS 2.7 nF
X7R
4.7 k
PC_BEEP
0.1 F
X7R
6.8 K +
AGND
Figure 13. Microphone Input
Figure 15. PC_BEEP Input
+5 VA +5 VA 8 1 4 68 k AGND AGND 100 k 2.7 k 4 3 5 2 1 220 pF AGND CGND AGND 47 k 220 pF + 6.8 k 10 F
AGND
U1A 3 MC33078D + 2 -
47 k
+ 10 F 47 k
AGND
47 k AGND 0.068 F X7R +5 VA U1B 8 MC33078D 5+ 1 F 7 6 MIC1/MIC2 X7R 4
220 pF
Figure 14. Microphone Pre-amplifier DS319-BQPP2 37 37
CS4299-BQ CS4299-BQ
6.1.5 Phone Input
MONO_OUT pins require 680 pF to 1000 pF NPO capacitors between the corresponding pin and analog ground. Each analog output is DC-biased up to the Vrefout signal reference, nominally 2.3 V. This requires the outputs be AC-coupled to external circuitry (AC load must be greater than 10 k) or DC coupled to a buffer op-amp biased at Vrefout.
One application of the PHONE input is to interface to the output of a modem analog front end (AFE) device so that modem dialing signals and protocol negotiations may be monitored through the audio system. Figure 16 shows a design for a modem connection where the output is fed from the CS4299-BQ MONO_OUT pin through a divider. The divider ratio shown does not attenuate the signal, providing an output voltage of 1 VRMS. If a lower output voltage is desired, the resistors can be replaced with appropriate values, as long as the total load on the output is kept greater than 10 k. The PHONE input is divided by 6 dB to accommodate a line-level source of 2 VRMS.
6.2.1
Stereo Outputs
See Figure 18 for a line-level stereo output reference design. See Figure 17 for a recommended headphone stereo output reference design.
6.2.2
Mono Output
6.2
Analog Outputs
The analog line-level output section provides two stereo outputs and a mono output. The LINE_OUT_L/R, ALT_LINE_OUT_L/R, and
6.8 k 0 1.0 F 1.0 F PHONE MONO_OUT 6.8 k 47 k 1000 pF
The mono output, MONO_OUT, can be either a sum of the left and right output channels, attenuated by 6 dB to prevent clipping at full scale, or the selected Mic signal. The mono out channel can drive the PC internal mono speaker using an appropriate buffer circuit
2 3 T DA1308 + 10 + HP_OUT_R 1/4 W ATT 1
PHONE MONO_OUT
22 pF NPO
220 F ELEC
ALT_LINE_OUT_R ALT_LINE_OUT_L 1000 pF NPO
1 2 27 k 1000 pF NPO
4 3
1 2 39 k
4 3 220 F ELEC + 10 HP_OUT_L 1/4 W ATT 4 3 47 k + T DA1308 7 1 2
22 pF NPO
6 AGND VREFOUT 0.1 F Y5V 5
1 F AGND
AGND
AGND
AGND
Figure 16. Modem Connection
Figure 18. Stereo Output
39 k 22 pF NPO
ALT_LINE_OUT_R Vrefout ALT_LINE_OUT_L
1000 pF NPO
2 27 k 3
+ TDA1308
1
+
220 F ELEC
10 1/4 Watt
Headphone Out
5 6 27 k 1000 pF NPO
+ -
7
+
220 F ELEC 47 k
10 1/4 Watt 47 k
22 pF NPO 39 k
AGND
AGND
Figure 17. Alternate Line Output as Headphone Output 38 38 DS319-BQPP2
CS4299-BQ CS4299-BQ
6.3 Miscellaneous Analog Signals 6.4 Power Supplies
The AFLT1 and AFLT2 pins must have a 1000 pF NPO capacitor to analog ground. These capacitors provide a single-pole low-pass filter at the inputs to the ADCs. This makes low-pass filters at each analog input pin unnecessary. The REFFLT pin must have a 1 F and a 0.1 F capacitor connected to analog ground with a short, wide trace to this pin (see Figure 21 in Section 8, Grounding and Layout, for an example). The 1 F capacitor must not be replaced with any value higher than 1 F. No other connection should be made, as any coupling onto this pin will degrade the analog performance of the CS4299-BQ. Likewise, digital signals should be kept away from REFFLT for similar reasons. The Vrefout pin is typically 2.3 V and provides a common mode signal for single-supply external circuits. Vrefout only supports light DC loads and should be buffered if AC loading is needed. For typical use the Vrefout pin should have a 1 F and a 0.1 F capacitor connected to analog ground.
The power supplies providing analog power should be as clean as possible to minimize coupling into the analog section which could degrade analog performance. The analog power pins, AVdd1 and AVdd2, supply power to all the analog circuitry on the CS4299-BQ. The +5 V analog supply should be generated from a linear voltage regulator (7805 type) connected to a +12 V supply. This helps isolate the analog circuitry from noise typically found on +5 V digital supplies. A typical voltage regulator circuit for analog power using a MC78M05CDT +5 V regulator is shown in Figure 19. The digital power pins, DVdd1 and DVdd2, should be connected to the same digital supply as the controller AC-link interface. The digital interface on the CS4299-BQ may operate at either +3.3 V or +5 V and proper connection of these pins will depend on the digital power supply of the controller.
6.5
Reference Design
See Section 11 for a CS4299-BQ reference design.
+12VD MC78M05CDT 1 + ELEC 10F IN GND 2 Y5V 0.1F OUT 3
+5VA
+ ELEC 10F
Y5V 0.1F
DGND
AGND
Figure 19. Voltage Regulator
DS319-BQPP2
39 39
CS4299-BQ CS4299-BQ
7. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF)
The S/PDIF digital output is used to interface the CS4299-BQ to consumer audio equipment external to the PC. This output provides an interface for storing digital audio data or playing digital audio data to digital speakers. Figure 20 illustrates the circuits necessary for implementing the IEC-958 optical or consumer interface. For further information on S/PDIF operation see application note AN22: Overview of Digital Audio Interface Data Structures [3]. For further information on S/PDIF recommended transformers see application note AN134: AES and S/PDIF Recommended Transformers [4]. of the CS4299-BQ and any other external analog circuitry. All analog components and traces should be located over the analog ground plane and all digital components and traces should be located over the digital ground plane. The common connection point between the two ground planes (required to maintain a common ground voltage potential) should be located under the CS4299-BQ. The AC-link digital interface connection traces should be routed such that the digital ground plane lies underneath these signals (on the internal ground layer). This applies along the entire length of these traces from the AC '97 controller to the CS4299-BQ. Refer to the Application Note AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices [2] for more information on layout and design rules.
8. GROUNDING AND LAYOUT
Figure 21 on page 41 shows the conceptual layout for the CS4299-BQ. The decoupling capacitors should be located physically as close to the pins as possible. Also note the connection of the REFFLT decoupling capacitors to the ground return trace connected directly to the ground return pin, AVss1. It is strongly recommended that separate analog and digital ground planes be used. Separate ground planes keep digital noise and return currents from modulating the CS4299-BQ ground potential and degrading performance. The digital ground pins should be connected to the digital ground plane and kept separate from the analog ground connections
SPDIF_OUT
S/PDIF_OUT
R1 R2 T1
J1 +5V_PCI 0.1 F
5
SPDIF_OUT 4 3 8.2 k 2 1
6
DGND
DVdd 3.3V 5V R1 247.5 375 R2 107.6 93.75
DGND
DGND
TOTX-173
DGND
Figure 20. S/PDIF Output 40 40 DS319-BQPP2
CS4299-BQ CS4299-BQ
Vrefout 1000 pF to via NPO
Via to +5VA
1 F
0.1 F Y5V
Via to +5VA
AFLT1 AVss1 REFFLT AVdd1
AFLT2
0.1 F Y5V
AVdd2
Via to Analog Ground Via to Analog Ground
Analog Ground
AVss2 Digital Ground
Via to Digital Ground
Pin 1 0.1 F Y5V DVss1
DVdd1
DVss2
0.1 F Y5V
DVdd2
Via to +5VD or +3.3VD Via to +5VD or +3.3VD
Figure 21. Conceptual Layout for the CS4299-BQ
DS319-BQPP2
41 41
CS4299-BQ CS4299-BQ
9. PIN DESCRIPTIONS
S/PDIF_OUT EAPD ID1# ID0# NC NC AVss2 ALT_LINE_OUT_R NC ALT_LINE_OUT_L AVdd2 MONO_OUT
48 47 46 45 44 43 42 41 40 39 38 37
DVdd1 XTL_IN XTL_OUT DVss1 SDATA_OUT BIT_CLK DVss2 SDATA_IN DVdd2 SYNC RESET# PC_BEEP
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
LINE_OUT_R LINE_OUT_L FLTO FLTI FLT3D BPCFG AFLT2 AFLT1 Vrefout REFFLT AVss1 AVdd1
CS4299-xQ
13 14 15 16 17 18 19 20 21 22 23 24 PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R
Figure 22. Pin Locations for the CS4299-BQ 42 42
(48-Pin LQFP)
DS319-BQPP2
CS4299-BQ CS4299-BQ
Audio I/O
PC_BEEP - Analog Mono Source, Input, Pin 12 The PC_BEEP input is intended to allow the PC system POST (Power On Self-Test) tones to pass through to the audio subsystem. The PC_BEEP input has two connections: the first connection is to the analog output mixer, the second connection is directly to the LINE_OUT stereo outputs. While the RESET# pin is actively being asserted and the BCFG pin is left floating, the PC_BEEP bypass path to the LINE_OUT outputs is enabled. While the CS4299-BQ is in normal operation mode, with RESET# deasserted or BCFG grounded, PC_BEEP is a monophonic source to the analog output mixer. The maximum allowable input is 1 VRMS (sinusoidal). This input is internally biased at the Vrefout voltage reference and requires AC-coupling to external circuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled to analog ground. PHONE - Analog Mono Source, Input, Pin 13 This analog input is a monophonic source to the analog output mixer. It is intended to be used as a modem subsystem input to the audio subsystem. The maximum allowable input is 1 VRMS (sinusoidal). This input is internally biased at the Vrefout voltage reference and requires AC-coupling to external circuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled to analog ground. MIC1 - Analog Mono Source, Input, Pin 21 This analog input is a monophonic source to the analog output mixer. It is intended to be used as a desktop microphone connection to the audio subsystem. The CS4299-BQ internal mixer's microphone input is MUX selectable with either MIC1 or MIC2 as the input. The maximum allowable input is 1 VRMS (sinusoidal). This input is internally biased at the Vrefout voltage reference and requires AC-coupling to external circuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled to analog ground. MIC2 - Analog Mono Source, Input, Pin 22 This analog input is a monophonic source to the analog output mixer. It is intended to be used as an alternate microphone connection to the audio subsystem. The CS4299-BQ internal mixer's microphone input is MUX selectable with either MIC1 or MIC2 as the input. The maximum allowable input is 1 VRMS (sinusoidal). This input is internally biased at the Vrefout voltage reference and requires AC-coupling to external circuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled to analog ground. LINE_IN_L, LINE_IN_R - Analog Line Source, Inputs, Pins 23 and 24 These inputs form a stereo input pair to the CS4299-BQ. The maximum allowable input is 1 VRMS (sinusoidal). These inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or both AC-coupled, with separate AC-coupling caps, to analog ground. CD_L, CD_R - Analog CD Source, Inputs, Pins 18 and 20 These inputs form a stereo input pair to the CS4299-BQ. It is intended to be used for the Red Book CD audio connection to the audio subsystem. The maximum allowable input is 1 VRMS (sinusoidal). These inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or both AC-coupled, with separate AC-coupling caps, to analog ground. CD_GND - Analog CD Common Source, Input, Pin 19 This analog input is used to remove common mode noise from Red Book CD audio signals. The impedance on the input signal path should be one half the impedance on the CD_L and CD_R input paths. This pin requires AC-coupling to external circuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled to analog ground. DS319-BQPP2 43 43
CS4299-BQ CS4299-BQ
VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17 These inputs form a stereo input pair to the CS4299-BQ. It is intended to be used for the audio signal output of a video device. The maximum allowable input is 1 VRMS (sinusoidal). These inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or both AC-coupled, with separate AC-coupling caps, to analog ground. AUX_L, AUX_R - Analog Auxiliary Source, Inputs, Pins 14 and 15 These inputs form a stereo input pair to the CS4299-BQ. The maximum allowable input is 1 VRMS (sinusoidal). These inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or both AC-coupled, with separate AC-coupling caps, to analog ground. LINE_OUT_L, LINE_OUT_R - Analog Line-Level, Outputs, Pins 35 and 36 These signals are analog outputs from the stereo output mixer. The full-scale output voltage for each output is nominally 1 VRMS (sinusoidal). These outputs are internally biased at the Vrefout voltage reference and require either AC-coupling to external circuitry or DC-coupling to a buffer op-amp biased at the Vrefout voltage. These pins need a 680-1000 pF NPO capacitor attached to analog ground. ALT_LINE_OUT_L, ALT _LINE_OUT_R - Analog Alternate Line-Level, Outputs, Pins 39 and 41 These signals are analog outputs from the stereo output mixer. The full-scale output voltage for each output is nominally 1 VRMS (sinusoidal). These outputs are internally biased at the Vrefout voltage reference and require either AC-coupling to external circuitry or DC-coupling to a buffer op-amp biased at the Vrefout voltage. These pins need a 680-1000 pF NPO capacitor attached to analog ground. MONO_OUT - Analog Mono Line-Level, Output, Pin 37 This signal is an analog output from the stereo-to-mono mixer or MIC1/2. The full-scale output voltage for this output is nominally 1 VRMS (sinusoidal). This output is internally biased at the Vrefout voltage reference and requires either AC-coupling to external circuitry or DC-coupling to a buffer op-amp biased at the Vrefout voltage. This pin needs a 680-1000 pF NPO capacitor attached to analog ground.
Clock and Configuration
XTL_IN - Crystal Input/Clock Input, Pin 2 In primary mode this pin requires either a 24.576 MHz crystal, with the other pin attached to XTL_OUT, or an external CMOS clock. The crystal frequency must be 24.576 MHz and designed for fundamental mode, parallel resonance operation. If an external CMOS clock is used to drive this pin, it must run at 24.576 MHz. In secondary mode all timing is derived from the BIT_CLK input signal and this pin should be left floating. XTL_OUT - Crystal Output, Pin 3 This pin is used when a crystal is placed between XTL_OUT and XLT_IN. If an external 24.576 MHz clock is used on XTL_IN, this pin must be left floating with no traces or components connected to it. In secondary mode this pin should be left floating. ID1#, ID0# - Codec ID, Inputs, Pins 45 and 46 These pins select the Codec ID and mode of operation for the CS4299-BQ. They are only sampled after the rising edge of RESET#. These pins are internally pulled up to the digital supply voltage and should be left floating for logic `0' or tied to digital ground for logic `1'. When both pins are left floating the CS4299-BQ is the primary codec. If either or both pins are tied to ground the CS4299-BQ is a secondary codec. 44 44 DS319-BQPP2
CS4299-BQ CS4299-BQ
Analog Reference, Filters, and Configuration
REFFLT - Internal Reference Voltage, Input, Pin 27 This signal is the voltage reference used internal to the CS4299-BQ. A 0.1 F and a 1.0 F (must not be larger than 1 F) capacitor with short, wide traces must be connected to this pin. No other connections should be made to this pin. Vrefout - Voltage Reference, Output, Pin 28 All analog inputs and outputs are centered around Vrefout, nominally 2.3 Volts. This pin may be used to level shift external circuitry. This pin cannot drive any DC loads, thus any external loading must be buffered. AFLT1 - Left ADC Channel Antialiasing Filter, Input, Pin 29 This pin needs a 1000 pF NPO capacitor connected to analog ground. AFLT2 - Right ADC Channel Antialiasing Filter, Input, Pin 30 This pin needs a 1000 pF NPO capacitor connected to analog ground. FLTI, FLTO - 3D Filter, Input, Pin 33 and 34 A 1000 pF capacitor must be connected between FLTI and FLTO if the 3D function is used. FLT3D - 3D Filter, Input, Pin 32 A 0.01 F capacitor must be connected from this pin to AGND if the 3D function is used. BCFG - Beep Configuration, Input, Pin 31 This pin is the configuration control for the PC_BEEP bypass path. If this pin is grounded, the bypass path is disabled. If this pin is left floating, the PC_BEEP bypass path is enabled.
Misc. Digital Interfaces
S/PDIF_OUT - Sony/Philips Digital Interface, Output, Pin 48 This pin generates the S/PDIF digital output from the CS4299-BQ when the SPEN bit in the S/PDIF Control Register (Index 68h) is `set'. This output may be used to directly drive a resistive divider and coupling transformer to an RCA-type connector for use with consumer audio equipment. EAPD - External Amplifier Powerdown, Output, Pin 47 This pin is used to control the powerdown state of an audio amplifier external to the CS4299-BQ. The output is controlled by the EAPD bit in the Powerdown Ctrl/Stat Register (Index 26h). It is driven as a normal CMOS output and defaults low (`0') upon power-up.
DS319-BQPP2
45 45
CS4299-BQ CS4299-BQ
AC-Link
RESET# - AC '97 Chip Reset, Input, Pin 11 This active low signal is the asynchronous Cold Reset input to the CS4299-BQ. The CS4299-BQ must be reset before it can enter normal operating mode. SYNC - AC-Link Serial Port Sync pulse, Input, Pin 10 This signal is the serial port timing signal for the AC-link. Its period is the reciprocal of the maximum sample rate, 48 kHz. The signal is generated by the controller, synchronous to BIT_CLK. SYNC is an asynchronous input when the CS4299-BQ is configured as a primary audio codec and is in a PR4 powerdown state. A series terminating resistor of 47 should be connected on the signal near the SYNC source. BIT_CLK - AC-Link Serial Port Master Clock, Input/Output, Pin 6 This input/output signal controls the master clock timing for the AC-link. In primary mode, this signal is a 12.288 MHz output clock derived from a 24.576 MHz crystal on the XTL_IN input clock. When the CS4299-BQ is in secondary mode, this signal is an input which controls the AC-link serial interface and generates all internal clocking including the AC-link serial interface timing and the analog sampling clocks. A series terminating resistor of 47 should be connected on this signal close to the CS4299-BQ in primary mode or close to the BIT_CLK source in secondary mode. SDATA_OUT - AC-Link Serial Data Input Stream to AC '97, Input, Pin 5 This input signal receives the control information and digital audio output streams. The data is clocked into the CS4299-BQ on the falling edge of BIT_CLK. A series terminating resistor of 47 should be connected on this signal near the controller. SDATA_IN - AC-Link Serial Data Output Stream from AC '97, Output, Pin 8 This output signal transmits the status information and digital audio input streams from the ADCs. The data is clocked out of the CS4299-BQ on the rising edge of BIT_CLK. A series terminating resistor of 47 should be connected on this signal as close to the CS4299-BQ as possible.
Power Supplies
DVdd1, DVdd2 - Digital Supply Voltage, Pins 1 and 9 Digital supply voltage for the AC-link section of the CS4299-BQ. These pins can be tied to +5 V digital or to +3.3 V digital. The CS4299-BQ and controller AC-link should share a common digital supply DVss1, DVss2 - Digital Ground, Pins 4 and 7 Digital ground connection for the AC-link section of the CS4299-BQ. These pins should be isolated from analog ground currents. AVdd1, AVdd2 - Analog Supply Voltage, Pins 25 and 38 Analog supply voltage for the analog and mixed signal sections of the CS4299-BQ. These pins must be tied to the analog +5 V power supply. It is strongly recommended that +5 V be generated from a voltage regulator to ensure proper supply currents and noise immunity from the rest of the system. AVss1, AVss2 - Analog Ground, Pins 26 and 42 Ground connection for the analog, mixed signal, and substrate sections of the CS4299-BQ. These pins should be isolated from digital ground currents. 46 46 DS319-BQPP2
CS4299-BQ CS4299-BQ
10. PARAMETER AND TERM DEFINITIONS
AC '97 Specification Refers to the Audio Codec '97 Component Specification Ver 2.1 published by the Intel(R) Corporation [6]. AC '97 Controller or Controller Refers to the control chip which interfaces to the audio codec AC-link. This has been also called DC '97 for Digital Controller '97 [6]. AC '97 Registers or Codec Registers Refers to the 64-field register map defined in the AC '97 Specification. ADC Refers to a single Analog-to-Digital converter in the CS4299-BQ. "ADCs" refers to the stereo pair of Analog-to-Digital converters. The CS4299-BQ ADCs have 18-bit resolution. Codec Refers to the chip containing the ADCs, DACs, and analog mixer. In this data sheet, the codec is the CS4299-BQ. DAC Refers to a single Digital-to-Analog converter in the CS4299-BQ. "DACs" refers to the stereo pair of Digital-to-Analog converters. The CS4299-BQ DACs have 20-bit resolution. dB FS A dB FS is defined as dB relative to full-scale. The "A" indicates an A weighting filter was used. Differential Nonlinearity The worst case deviation from the ideal code width. Units in LSB. Dynamic Range (DR) DR is the ratio of the RMS full-scale signal level divided by the RMS sum of the noise floor, in the presence of a signal, available at any instant in time (no change in gain settings between measurements). Measured over a 20 Hz to 20 kHz bandwidth with units in dB FS A. FFT Fast Fourier Transform. Frequency Response (FR) FR is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The amplitude corner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The listed minimum and maximum frequencies are guaranteed to be within the Ac from minimum frequency to maximum frequency inclusive. Fs Sampling Frequency. Interchannel Gain Mismatch For the ADCs, the difference in input voltage to get an equal code on both channels. For the DACs, the difference in output voltages for each channel when both channels are fed the same code. Units are in dB. DS319-BQPP2 47 47
CS4299-BQ CS4299-BQ
Interchannel Isolation The amount of 1 kHz signal present on the output of the grounded AC-coupled line input channel with 1 kHz, 0 dB, signal present on the other line input channel. Units are in dB. Line-level Refers to a consumer equipment compatible, voltage driven interface. The term implies a low driver impedance and a minimum 10 k load impedance. Paths A-D: Analog in, through the ADCs, onto the serial link. D-A: Serial interface inputs through the DACs to the analog output. A-A: Analog in to Analog out (analog mixer). PC 99 Refers to the PC 99 System Design Guide published by the Microsoft(R) Corporation [7]. PLL Phase Lock Loop. Circuitry for generating a desired clock from an external clock source. Resolution The number of bits in the output words to the DACs, and in the input words to the ADCs. Signal to Noise Ratio (SNR) SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the noise floor, in the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with units in dB. S/PDIF Sony/Phillips Digital Interface. This interface was established as a means of digitally interconnecting consumer audio equipment. The documentation for S/PDIF has been superseded by the IEC-958 consumer digital interface document. SRC Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The CS4299-BQ operates at a fixed sample frequency of 48 kHz. The internal sample rate converters are used to convert digital audio streams playing back at other frequencies to 48 kHz. Total Harmonic Distortion plus Noise (THD+N) THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMS full-scale signal level. It is tested using a -3 dB FS input signal and is measured over a 20 Hz to 20 kHz bandwidth with units in dB FS. 48 48 DS319-BQPP2
+12V C1 X7R
IN GND OUT 1 3
U1
MC78M05ACDT
+5VA
PC SPEAKER IN
0.1uF + 6.8K X7R ELEC X7R X7R ELEC 2700pF 10uF 0.1uF
2
R1
47K
J1 + C3 0.1uF 10uF C4 C5 C6
1
9
26
42
R6
4 7 DVss2 DVss1 DVdd1 DVdd2 AVss1 AVss2 AVdd1 AVdd2
6.8K
4X1HDR-AU
25 38
1uF C16
24 23 LINE_IN_R LINE_IN_L MIC1 MIC2 VIDEO_R VIDEO_L PHONE Vrefout REFFLT AFLT1 FLTI FLTO XTL_IN AFLT2 FLT3D 33 34 nc5 nc6 nc7 S/PDIF_OUT 2 3 ID0# ID1# BCFG EAPD MONO_OUT 37 31 47 45 46 40 43 44 48 ALT_LINE_OUT_L 21 22 17 16 13 CD_L 39 ALT_LINE_OUT_R
19 18 CD_GND 41
+
+
R16 C21 6.8K Y5V
6.8K
1uF
PHONO-1/8
R17
C22 1uF Y5V +5VA X7R Y5V X7R NPO NPO X7R 0.1uF 1uF 0.1uF 1000pF 1000pF 0.01uF
C23
C24
C25
C26
C27
C28
C29 1000pF NPO
XTL_OUT
DS319-BQPP2
R2 C2 AGND AGND 6.8K C7 6.8K C8 0.1uF 6.8K C12 U3 Y5V 1uF X7R X7R X7R X7R 0.1uF 0.1uF 0.1uF C9 C10 C11 Y5V 1uF +3.3VD
2
1
2X1HDR-SN/PB
DGND
AGND
AUX IN
R3
J2
R4
4
3
2
R5
11. REFERENCE DESIGN
1
AC LINK
PCI Audio Controller
AGND
6
AGND 1uF C13
BIT_CLK
AGND Y5V DGND 100K
SDATA_IN SDATA_OUT 8 5
CS4299 R7 R8 47 47
or ICH Controller
ABITCLK ASDOUT ASDIN ASYNC ARST#
CD IN
1uF C14
14 AUX_R AUX_L CD_R LINE_OUT_L 35 LINE_OUT_R 36 12 15 20 PC_BEEP RESET# SYNC 11 10
R9
J3
4
3
Y5V
LINE OUT
C15 10uF ELEC C17 10uF ELEC
4 3 5 2 1
2
1
R10 Y5V
100K
J4
4X1HDR-AU 100K
R11
R12 C19 1000pF NPO C18 1000pF NPO 220K
R13 220K PHONO-1/8
LINE IN
6.8K C20
27
AGND 1uF Y5V
29 30 32 28
J5
R14
4
3
AGND
AGND
AGND
AGND
AGND
5
R15
6.8K
2
1
S/PDIF OUT
J6
4 3 2
MIC IN
1.5K 60 mil trace
AGND
AGND
J7
R18
2.2K
R19
4
3
+5VD 100 C30 DGND Tie at one point only under the codec C33 NPO 22pF C34 22pF NPO C31 0.1uF X7R AGND Y5V 24.576 MHz (50 PPM) 1uF GND_TIE Y1 R21 6.8K
5
R20
1 5 6
2
1
PHONO-1/8
+
TOTX-173
C32
10uF
ELEC
AGND
AGND
AGND
DGND
DGND
DGND
DGND
Figure 23. CS4299 Reference Design
CS4299-BQ CS4299-BQ
49 49
CS4299-BQ CS4299-BQ
12. REFERENCES
1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997 http://www.cirrus.com/products/papers/meas/meas.html 2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998 3) Cirrus Logic, AN22: Overview of Digital Audio Interface Data Structures, Version 2.0, February 1998 4) Cirrus Logic, AN134: AES and S/PDIF Recommended Transformers, Version 2, April 1999 5) Cirrus Logic, AN165: CS4297A/CS4299 EMI Reduction Techniques, Version 1.0, September 1999 6) Intel(R), Audio Codec '97 Component Specification, Revision 2.1, May 1998 http://developer.intel.com/ial/scalableplatforms/audio/index.htm 7) Microsoft(R), PC 99 System Design Guide, Version 1.0, July 1999 http://www.microsoft.com/hwdev/desguid/ 8) Intel(R) 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub, June 1999 http://developer.intel.com/design/chipsets/datashts/290655.htm
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DS319-BQPP2
CS4299-BQ CS4299-BQ
13. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
INCHES NOM 0.055 0.004 0.009 0.354 0.28 0.354 0.28 0.020 0.24 4 MILLIMETERS NOM 1.40 0.10 0.22 9.0 BSC 7.0 BSC 9.0 BSC 7.0 BSC 0.50 BSC 0.60 4
MIN --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000 * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS022
DIM A A1 B D D1 E E1 e* L
MAX 0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000
MIN --0.05 0.17 8.70 6.90 8.70 6.90 0.40 0.45 0.00
MAX 1.60 0.15 0.27 9.30 7.10 9.30 7.10 0.60 0.75 7.00
DS319-BQPP2
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